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toshiba toshiba corporation 1/12 tlcs-90 series TMP90C141 the information contained here is subject to change without notice. the information contained herein is presented only as guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. these toshiba products are intended for usage in general electronic equipments (of?e equipment, communication equipment, measuring equipment, domestic electri?ation, etc.) please make sure that you consult with us before you use these toshiba products in equip- ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traf? signal, combustion control, all types of safety devices, etc.). toshiba cannot accept liability to any damage which may occur in case these toshiba products were used in the mentioned equipments without prior consultation with toshiba. cmos 8?it microcontrollers TMP90C141n/TMP90C141f 1. outline and characteristics the TMP90C141 is a high-speed advanced 8-bit microcontroller applicable to a variety of equipment. with its 8-bit cpu, a/d converter, multi-function timer/ event counter and general-purpose serial interface integrated into a single cmos chip, the tmp90c041 allows the expansion of external memories for programs (up to 64k byte) and data (1m byte). the TMP90C141n is a 64-pin shrink dip product. (sdip64-p750) the tmp90c041f is a 64-pin ?t package product. (qfp64-p1420a) the characteristics of the TMP90C141 include: (1) powerful instructions: 163 basic instructions, including multiplication, division, 16-bit arithmetic operations, bit manipulation instructions (2) minimum instruction executing time: 320ns (at 12.5mhz oscillation frequency) (3) internal ram (4) memory expansion external program memory: 63k byte external data memory: 1m byte (5) 8-bit a/d converter (6 channels) (6) general-purpose serial interface (1 channel) asynchronous mode, i/o interface mode (7) multi-function 16-bit timer/event counter (1 channel) (8) 8-bit timers (4 channels) (9) stepping motor control port (2 channels) (10) input/output ports (28 pins) (11) interrupt function:10 internal interrupts and 4 external interrupts (12) micro direct memory access ( m dma) function (11 channels) (13) watchdog timer (14) standby function (4 halt modes)
2/12 toshiba corporation TMP90C141 figure 1. TMP90C141 block diagram
toshiba corporation 3/12 TMP90C141 2. pin assignment and functions the assignment of input/output pins, their names and functions are described below. 2.1 pin assignment figure 2.1 (1) shows pin assignment of the TMP90C141n. figure 2.1 (1). pin assignment (shrink dual inline package)
4/12 toshiba corporation TMP90C141 figure 2.1 (2) shows pin assignment of theTMP90C141f. figure 1. 1 (2). pin assignment (flat package) 2.2 pin names and functions the names of input/output pins and their functions are summa- rized in t able 2.2. table 2.2 pin names and functions (1/2) pin name no. of pins i/o 3 states function d0 ~ d7 8 3 states data bus: also functions as 8-bit bidirectional data bus for external memory a0 ~ a7 8 output address bus: the lower 8 bits address bus for external memory a8 ~ a15 8 output address bus: the upper 8 bits address bus for external memory p30 /rxd 1 input port 30: 1-bit input port receiver serial data p31 /rxd 1 input port 31: 1-bit input port receiver serial data p32 /txd /r ts /sclk 1 output port 32: 1-bit input port transmitter serial data request to send serial data serial clock output p33 /txd 1 output port 33: 1-bit output port transmitter serial data p34 /cts 1 input port 34: 1-bit input port clear to send serial data rd 1 output read: generates strobe signal for reading external memory wr 1 output write: generates strobe signal for writing into external memory p37 /w ait 1 input port 37: 1-bit input port wait: input pin for connecting slow speed memory or peripheral lsi p40 ~ p43 /a16 ~ a19 4 output port 4: 4-bit output port that allows selection of port/address bus on bit basis address bus: also functions as address bus for external memory (4 bits of bank address)
toshiba corporation 5/12 TMP90C141 table 2.2 pin names and functions (2/2) pin name no. of pins i/o 3 states function p50 ~ p55 /an0 ~ an5 6 input port 5: 6-bit input port analog input: 6 analog input to a/d converter vref 1 input of reference voltage to a/d converter agnd 1 ground pin for a/d converter p60 ~ p63 /m00 ~ m03 /to1 4 i/o port 6: 4-bit i/o port that allows i/o selection on bit basis output stepping motor control port 0 output t imer output 1: output of timer 0 or 1 p70 ~ p73 /m10 ~ m13 /to3 4 i/o port 7: 4-bit i/o port that allows i/o selection on bit basis output stepping motor control port 1 output t imer output 3: output of timer 2 or 3 p80 /into 1 input port 80: 1-bit input port interrupt request pin 0: interrupt request pin (level/rising edge is programmable) p81 /int1 /ti4 1 input port 81: 1-bit input port interrupt request pin 1: interrupt request pin (rising/falling edge is programmable) timer input 4: counter/capture trigger signal for timer 4 p82 /int2 /ti5 1 input port 82: 1-bit input port interrupt request pin 2: rising edge interrupt request pin timer input 5: capture trigger signal for timer 4 p82 /to3/t04 1 output port 83: 1-bit output port timer output 3/4: output of timer 2, 3 or 4 nmi 1 input non-maskable interrupt request pin: falling edge interrupt request pin clk 1 output clock output: generates clock pulse at 1/4 frequency of clock oscillation. it is pulled up internally during resetting. ea 1 input external access: connects with gnd pin in the TMP90C141 with no internal rom. reset 1 input reset: initializes the TMP90C141. (built-in pull-up resister) x1/x2 2 input/ output pin for quartz crystal or ceramic resonator v cc 1 power supply (+5v) v ss (gnd) 1 ground (0v)
6/12 toshiba corporation TMP90C141 3. operation the following explains the TMP90C141 functions and basic operations. the cpu functions and internal i/o functions of the TMP90C141 are the same as the tmp90c840a. refer to the ?mp90c840a?section concerning functions which are not explained the following. 3.1 cpu the TMP90C141 has an internal high-performance 8-bit cpu. refer to the ?lcs-90 cpu?section concerning cpu operation. 3.2 memory map the TMP90C141 supports a program memory of up to 64k bytes and a data memory of maximum 1m bytes. the program memory may be assigned to the address space from 00000h to 0ffffh, while the data memory can be allocated to any address from 00000h to fffffh. (1) internal ram the TMP90C141 internally contains a 1k byte ram, which is allocated to the address space from fbc0h to ffbfh. the cpu allows the access to a certain ram area (ff00h to ffbfh, 192 bytes) by a short operation code (opcode) in a ?irect addressing mode? the addresses from ff10h to ff7fh in this ram area can be used as parameter area for micro dma processing (and for any other purposes when the micro dma function is not used). (2) internal i/o the TMP90C141 provides a 48-byte address space as an internal i/o area, whose addressess range from ffc0h to ffefh. this i/o area can be accessed by the cpu using a short opcode in the ?irect addressing mode? figure 3.1 is a memory map indicating the areas accessible by the cpu in the respective addressing mode.
toshiba corporation 7/12 TMP90C141 figure 3.2. memory map
8/12 toshiba corporation TMP90C141 4. electrical characteristics TMP90C141n/TMP90C141f note: i dar is guaranteed for a total of up to 8 optional ports. 4.1 absolute maximum ratings symbol parameter rating unit v cc supply voltage -0.5 ~ + 7 v v in input voltage -0.5 ~ v cc + 0.5 v p d power dissipation (ta = 70 c) f 500 mw n 600 t solder soldering temperature (10s) 260 c t stg storage temperature -65 ~ 150 c t opr operating temperature -20 ~ 70 c 4.2 dc characteristics ta = -20 ~ 70 c vcc = 5v 10% typical values are for ta = 25 c and v cc = 5v. symbol parameter min max unit test conditions v il input low voltage (d0 ~ d7) -0.3 0.2v cc - 0.1 v v il1 p3, p5, p6, p7, p8 -0.3 0.3v cc v v il2 reset , int0, nmi -0.3 0.25v cc v v il4 x1 -0.3 0.2v cc v v ih input low voltage (d0 ~ d7) 0.2v cc + 1.1 v cc + 0.3 v v ih1 p3, p5, p6, p7, p8 0.7v cc v cc + 0.3 v v ih2 reset , int0, nmi 0.75v cc v cc + 0.3 v v ih4 x1 0.8v cc v cc + 0.3 v v ol output low voltage 0.45 v i ol = 1.6ma v oh v oh1 v oh2 output high voltage 2.4 0.75v cc 0.9v cc v v v i oh = -400 m a i oh = -100 m a i oh = -20 m a i dar darlington drive current (8 i/o pins) -1.0 -3.5 ma v ext = 1.5v r ext = 1.1k w i li input leakage current 0.02 (typ) 5 m a 0.0 vin v cc i lo output leakage current 0.05 (typ) 10 m a 0.2 vin v cc - 0.2 i cc operating current (run) idle 1 idle 2 20 (typ) 1.5 (typ) 9 (typ) 30 5 15 ma ma ma tosc = 12.5mhz stop (ta = -20 ~ 70 c) stop (ta = 0 ~ 50 c) 0.2 (typ) 50 10 m a m a 0.2 vin v cc - 0.2 r rst reset pull up register 50 150 k w cio pin capacitance 10 pf testfreq = 1mhz v th schmitt width reset , nmi , int0 0.4 1.0 (typ) v
toshiba corporation 9/12 TMP90C141 ac output level high 2.2v/low 0.8v ac input level high 2.4v/low 0.45v (d0 ?d7) high 0.8v cc /low 0.2v cc (excluding d0 ?d7) 4.3 ac characteristics ta = -20 ~ 70 cv cc = 5v 10% cl = 50pf symbol parameter variable 10mhz clock 12.5mhz clock unit min max min max min max t osc osc. period = x 80 1000 100 80 ns t cyc clk period 4x 4x 400 320 ns t wl clk low width 2x - 40 160 120 ns t wh clk high width 2x - 40 160 120 ns t ac address setup to rd , wr x - 45 55 35 ns t rr rd low width 2.5x - 40 210 160 ns t ca address hold time after rd , wr 0.5x - 30 20 10 ns t ad address to valid data in 3.5x - 95 255 185 ns t rd rd to valid data in 2.5x - 80 170 120 ns t hr input data hold after rd 0 0?ns t ww wr low width 2.5x - 40 210 160 ns t dw data setup to wr 2x - 50 150 110 ns t wd data hold after wr 30 90 30 90 30 90 ns t cwa rd , wr to valid wait 1.5x - 100 50 20 ns t awa address to valid wait 2.5x - 130 120 70 ns t was wait setup to clk 70 70 70 ns t wah wait hold after clk 0 0 0 ns t rv rd /wr recovery time 1.5x - 35 115 85 ns t cpw clk to port data output x + 200 300 280 ns t prc port data setup to clk 200 200 200 ns t cpr port data hold after clk 100 100 100 ns t chcl rd /wr hold after clk x - 60 40 20 ns t clc rd /wr setup to clk 1.5x - 50 100 70 ns t clha address hold after clk 1.5x - 80 70 40 ns t acl address setup to clk 2.5x - 80 170 120 ns t cld data setup to clk x - 50 50 30 ns
10/12 toshiba corporation TMP90C141 4.4 a/d conversion characteristics ta = -20 ~ 70 c v cc = 5v 10% symbol parameter min typ max unit v ref analog reference voltage v cc - 1.5 v cc v cc v a gnd analog reference voltage v ss v ss v ss v ain allowable analog input voltage v ss ? cc i ref supply current for analog reference voltage 0.5 1.0 ma error total error (ta = 25 c, v cc = v ref = 5.0v) 1.0 lsb total error 2.5 4.5 zero-cross characteristics ta = -20 ~ 70 c v cc = 5v 10% symbol parameter condition min max unit v zx zero-cross detection input ac coupling c = 0.1 m f 1 1.8 vac p - p a zx zero-cross accuracy 50/60hz sine wave 135 mv f zx zero-cross detection input frequency 0.04 1 khz 4.6 serial channel timing-i/o interface mode ta = -20 ~ 70 c v cc = 5v 10% cl = 50pf symbol parameter variable 10mhz clock 12.5mhz clock unit min max min max min max t scy serial port clock cycle time 8x 800 640 ns t oss output data setup sclk rising edge 6x - 150 450 330 ns t ohs output data hold after sclk rising edge 2x - 120 80 40 ns t hsr input data hold after sclk rising edge 0 0?ns t srd sclk rising edge to input data valid 6x - 150 450 330 ns 4.7 16-bit event counter ta = -20 ~ 70 c v cc = 5v 10% symbol parameter variable 10mhz clock 12.5mhz clock unit min max min max min max t vck ti4 clock cycle 8x + 100 900 740 ns t vckl ti4 low clock pulse width 4x + 40 440 360 ns t vckh ti4 high clock pulse width 4x + 40 440 360 ns
toshiba corporation 11/12 TMP90C141 (reference) de?ition of i dar 4.9 i/o interface mode timing chart 4.8 interrupt operation ta = -20 ~ 70 c v cc = 5v 10% symbol parameter variable 10mhz clock 12.5mhz clock unit min max min max min max t intal nmi , int0 low level pulse width 4x 400 320 ns t intah nmi , int0 high level pulse width 4x 400 320 ns t intbl int1, int2 low level pulse width 8x + 100 900 740 ns t intbh int1, int2 high level pulse width 8x + 100 900 740 ns
12/12 toshiba corporation TMP90C141 4.10 timing chart 5. differences between tmp90c841a and TMP90C141 speci?ations of tmp90c841a and TMP90C141 are the same except below. * note: connect ea pin with gnd pin. name tmp90c841a TMP90C141 ram 256 bytes of internal ram are provided. (0fec0h ~ 0ffbfh) 1024 bytes of internal ram are provided. (0fbc0h ~ 0ffbfh) a0 ~ a15 high-impedance state during reset driving state during reset. p0 (0ffc1h) p1 (0ffc1h) p2 (0ffc4h) provided (same chip as tmp90c840a) r/w function is not provided. p01cr (0ffc2h) provided ext, p1c, p0c is not provided. p2cr (0ffc5h) provided p2xc register is not provided

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